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Embedded Electronics Engineering students' contributions to publications

We encourage students to participate in our research projects. The articles to which our students have contributed are listed below.

2016

Jing ZHANG (Lund University - Sweden), Lars Johan FRITZ (Ericsson - Sweden), Liang LIU, Erik LARSSON (Lund University - Sweden): Compressor design for silicon debug (presented at the European Test Symposium (ETS) in Amsterdam in May 2016)

2015

Chu, N. Deo, W. Ahmad, M. Törmänen, H. Sjöland, “An Ultra-low Power Charge-Pump PLL with High Temperature Stability in 130nm CMOS”, IEEE International New Circuits and Systems Conference (NEWCAS), Grenoble, France, 2015-06-07.

N. Deo, J. Wernehag, J. Thelberg: Low power, highly stable and wideband LNA for GNSS applications in SiGe technology; Norcas, Oslo, Norway, 2015-10-26/2015-10-28. (In press) (BibTeX)

2014

M. Khorramnejadi, A. Nejdel, M. Liliebladh, H. Sjöland, "Design of a 2.45GHz Wireless Temperature Sensor in 130nm CMOS Technology", IEEE International Conference on New Circuits and Systems (NEWCAS), Canada, June 2014.

A. Jin, S. Fu, A. Sakurai, L. Liu, F. Edman, T. Pullerits, V. Öwall, K. Karki: High precision measurements using high frequency gigahertz signals, Review of Scientific Instruments, Vol. 85, No. 12, 2014.

D. Dasalukunte, S. Mehmood, V. Öwall: Complexity analysis of IOTA filter architectures in Faster-than-Nyquist multicarrier systems NORCHIP, Lund, 2011-11-14.

Peter Nilsson, Ateeq Ur Rahman Shaik, Rakesh Gangarajaiah, and Erik Hertz, “Hardware Implementation of the Exponential Function Using Taylor Series,” in the Proceedings of the 32nd NORCHIP Conference, Tampere, Finland, October 27-28, 2014.

Peter Nilsson, Mohammed Azher Ali, Manivannan Ethiraj, and S. M. Yasser Sherazi, “Supply-Voltage Down Conversion for Digital CMOS Designs,” in the Proceedings of the IEEE 21th International Conference on Electronics, Circuits and Systems (ICECS 2014), Marseille, France, December 7–10, 2014.

2013

C. Müller, S. Malkowsky, O. Andersson, B. Mohammadi, J. Sparso, J. Rodrigues: A 65-nm CMOS Area Optimized De-synchronization Flow for sub-V-T Designs, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC), Istanbul, TURKEY, pp. 380-385, OCT 07-09, 2013.

S. Yan, M. Andersson, H. Sjöland, “A 31.25/125MSps Continuous-Time Delta-Sigma ADC with 64/59dB SNDR in 130nm CMOS”,NORCHIP, Vilnius, Lithuania, Nov. 2013.

S. Mehmood, D. Dasalukunte, V. Öwall: Hardware architecture of IOTA pulse shaping filters for multicarrier systems Transactions on Circuits and Systems - I, Regular papers, Vol. 60, No. 3, pp. 733-742, 2013.

M. Al-Obaidi, H. Kittur, H. Andersson, V. Öwall: Hardware Acceleration of the Robust Header Compression (RoHC) Algorithm, IEEE ISCAS, Beijing, pp. 293-296, 2013-05-19.

S. Granlund, L. Liu, C. Zhang, V. Öwall: Implementation of a Highly-Parallel Soft-Output MIMO Detector with Fast Node Enumeration NORCHIP, Vilnius, Lithuania, 2013-11-11/2013-11-12.

Peter Nilsson, Anusha Gundarapu, and S. M. Yasser Sherazi, “Power Savings in Digital Filters for Wireless Communication,” in the Proceedings of the European Conference on Circuit Theory and Design (ECCTD 2013), September 8-12, 2013, pp., Dresden, Germany.

2012

A. Karlsson, O. Andersson, J. Sparsø, J. Rodrigues: IR-Drop Reduction in Sub-VT Circuits by De-synchronization, 2012 IEEE Subthreshold Microelectronics Conference (SubVT), IEEE Subthreshold Microelectronics Conference, IEEE-Sub-Vt 2012, Waltham, Massachusetts, USA, 2012-10-09/2012-10-10.

2011

I. Diaz, B. Sathyanarayanan, A. Malek, F. Foroughi, J. Rodrigues: Highly Scalable Implementation of a Robust MMSE Channel Estimator for OFDM Multi-Standard Environment, IEEE Workshop on Signal Processing Systems, Beirut, Lebanon, pp. 311-315, 2011-10-4/7.

H. Prabhu, S. Thomas, J. Rodrigues, T. Olsson, A. Carlsson: A GALS ASIC implementation from a CAL dataflow description, IEEE, NORCHIP, Lund, Sweden, 2011-11-14/2011-11-15.

X. Liu, V. Viswam, J. Wernehag, I. ud Din, P. Andreani: Highly linear direct conversion receiver using customized on-chip balun, NORCHIP, Lund, Sweden, 2011-11-14/2011-11-15.

A. Nejdel, M. Törmänen, H. Sjöland: A linearized 1.6-5 GHz low noise amplifier using positive feedback in 65 nm CMOS NORCHIP 2011, Lund, Sweden, 2011-11-14/2011-11-15. 2011.

K. K. Lee, C. Bryant, M. Törmänen, H. Sjöland:Design and analysis of an ultra-low-power LC quadrature VCO, Analog Integrated Circuits and Signal Processing, Vol. 67, pp. 49-60

A. Nejdel, M. Törmänen, H. Sjöland: A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback, Analog Integrated Circuits and Signal Processing, Vol. 74, No. 1, pp. 47-57

Y. Wu, X. Liu, D. Ye, V. Viswam, L. Zhu, P. Lu, D. Radjen, H. Sjöland, ”A 0.13µm CMOS Delta-Sigma PLL FM Transmitter”, Norchip, Lund, Sweden, Nov. 2011.

Peter Nilsson and Syed Nadeemuddin, “Power Reductions in Unrolled CORDIC Architectures,” in the Proceedings of the European Conference on Circuit Theory and Design (ECCTD 2011), August 29-31, 2011, pp. 725-728, Linköping, Sweden.

Peyman Pouyan, Erik Hertz, and Peter Nilsson, “A VLSI Implementation of Logarithmic and Exponential Functions Using a Novel Parabolic Synthesis Methodology Compared to the CORDIC Algorithm,” in the Proceedings of the European Conference on Circuit Theory and Design (ECCTD 2011), August 29-31, 2011, pp. 729-732, Linköping, Sweden.

2010

M. Stala, C. Bilgin, R. Gangarajaiah, J. Rodrigues: Hardware Implementation of an Iterative Sampling Rate Converter for Wireless Communication IEEE Global Telecommunications Conference (Globecom), IEEE GLOBECOM 2010, Miami, Florida, USA, 2010-12-04.