The browser you are using is not supported by this website. All versions of Internet Explorer are no longer supported, either by us or Microsoft (read more here: https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Please use a modern browser to fully experience our website, such as the newest versions of Edge, Chrome, Firefox or Safari etc.

Re-using Chip Level DFT at Board Level

På svenska

Author

  • Xinli Gu
  • Jeff Rearick
  • Bill Eklow
  • Jun Qian
  • Artur Jutman
  • Krishnendu Chakrabarty
  • Erik Larsson

Summary, in English

As chips are getting increasingly complex, there is no surprise to find more and more built-in DFX. This built-in DFT is obviously beneficial for chip/silicon DFX engineers; however, board/system level DFX engineers often have limited access to the build in DFX features. There is currently an increasing demand from board/system level DFX engineers to reuse chip/silicon DFX at board/system level. This special session will discuss: What chip access is needed for board-level for test and diagnosis? How to accomplish the access? Will IEEE P1687 and IEEE 1149.1 solve these problems?

Publishing year

2012

Language

English

Pages

205-205

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Board test
  • board diagnosis
  • chip access
  • IEEE P1687
  • IEEE 1149.1

Conference name

European Test Symposium, 2012

Conference date

2012-05-28 - 2012-05-28

Conference place

Annecy, France

Status

Published

Research group

  • Digital ASIC