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Digital implementation of a wavelet-based event detector for cardiac pacemakers

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Author

Summary, in English

This paper presents a digital hardware implementation of a novel wavelet-based event detector suitable for the next generation of cardiac pacemakers. Significant power savings are achieved by introducing a second operation mode that shuts down 2/3 of the hardware for long time periods when the pacemaker patient is not exposed to noise, while not degrading performance. Due to a 0.13-mu m CMOS technology and the low clock frequency of 1 kHz, leakage power becomes the dominating power source. By introducing sleep transistors in the power-supply rails, leakage power of the hardware being shut off is reduced by 97%. Power estimation on RTL-level shows that the overall power consumption is reduced by 67% with a dual operation mode. Under these conditions, the detector is expected to operate in the sub-mu W region. Detection performance is evaluated by means of databases containing electrograms to which five types of exogenic and endogenic interferences are added. The results show that reliable detection is obtained at moderate and low signal to noise-ratios (SNRs). Average detection performance in terms of detected events and false alarms for 25-dB SNR is P-D = 0.98 and P-FA = 0.014, respectively.

Publishing year

2005

Language

English

Pages

2686-2698

Publication/Series

IEEE Transactions on Circuits and Systems Part 1: Fundamental Theory and Applications

Volume

52

Issue

12

Document type

Journal article

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • cardiac pacemaker
  • event detector
  • gated supply
  • sleep transistors
  • wavelet filter

Status

Published

ISBN/ISSN/Other

  • ISSN: 1057-7122