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Integrated Test Scheduling, Test Parallelization and TAM Design

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Author

Summary, in English

We propose a technique integrating test scheduling, scan chain partitioning and test access mechanism (TAM) design minimizing the test time and the TAM routing cost while considering test conflicts and power constraints. Main features of our technique are (1) the flexibility in modelling the systems test behaviour and (2) the support for interconnection test of unwrapped cores and user-defined logic. Experiments using our implementation on several benchmarks and industrial designs demonstrate that it produces high quality solution at low computational cost.

Publishing year

2002

Language

English

Pages

397-404

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • test access mechanism
  • TAM
  • TAM routing
  • test scheduling
  • scan chain partitioning
  • test conflicts
  • power constraints

Conference name

IEEE Asian Test Symposium ATS02

Conference date

2002-11-18 - 2002-11-20

Conference place

Guam, United States

Status

Published

ISBN/ISSN/Other

  • ISSN: 1081-7735
  • ISBN: 0-7695-1825-7