Test Scheduling for Modular SOCs in an Abort-on-Fail Environment

Summary, in English

Complex SOCs areincreasingly tested in a modular fashion, which enables us torecord the yield-per-module. In this paper, we consider theyield-per-module as the pass probability of the module smanufacturing test. We use it to exploit the abort-on-fail featureof ATEs, in order to reduce the expected test application time. Wepresent a model for expected test application time, which obtainsincreasing accuracy due to decreasing granularity of the abortabletest unit. For a given SOC, with a modular test architectureconsisting of wrappers and disjunct TAMs, and for given passprobabilities per module test, we schedule the tests on each TAMsuch that the expected test application time is minimized. Wedescribe two heuristic scheduling approaches, one without and onewith preemption. Experimental results for the ITC 02 SOC TestBenchmarks demonstrate the effectiveness of our approach, as weachieve up to 97% reduction in the expected test application time,without any modification to the SOC or ATE.

• Author: Urban Ingelsson; Sandeep Kumar Goel; Erik Larsson; Erik Jan Marinissen
• Publishing year: 2005
• Language: English
• Pages: 8-13
• Publication/Series: [Host publication title missing]
• Links: http://dx.doi.org/10.1109/ETS.2005.38
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Keywords: testing; systems-on-chip; yield-per-module; TAM; test scheduling
• Conference name: IEEE European Test Symposium ETS 05, 2005
• Conference date: 2005-05-22 - 2005-05-25
• Conference place: Tallinn, Estonia
• Status: Published
• ISBN/ISSN/Other: ISBN: 0-7695-2341-2