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Preemptive system-on-chip test scheduling

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Author

Summary, in English

In this paper, we propose a preemptive test scheduling technique (a test can be interrupted and later resumed) for core-based systems with the objective to minimize the test application time. We make use of reconfigurable core test wrappers in order to increase the flexibility in the scheduling process. The advantage with such a wrapper is that it is not limited to a single TAM (test access mechanism) bandwidth (wrapper chain configuration) at each core. We model the scheduling problem as a Bin-packing problem, and we discuss the transformation: number of TAM wires (wrapper-chains) versus test time in combination with preemption, as well as the possibilities and the limitations to achieve an optimal solution in respect to test application time. We have implemented the proposed preemptive test scheduling algorithm, and we have through experiments demonstrated its efficiency.

Publishing year

2004

Language

English

Pages

620-629

Publication/Series

IEICE Transactions on Information and Systems

Volume

E87D

Issue

3

Document type

Journal article

Publisher

The Institute of Electronics, Information and Communication Engineers

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • test scheduling
  • test access mechanism design
  • preemptive scheduling
  • system-on-chip testing

Status

Published

ISBN/ISSN/Other

  • ISSN: 0916-8532