Hardware Architectures for Wireless Communication - Symbol Detection and Channel Estimation
Author
Summary, in English
In this thesis different aspects of baseband implementation of mobile communication systems is treated. The content is focused on symbol detection and channel estimation in MIMO and OFDM. The thesis deals with the complete chain from algorithm to silicon implementation within these areas.
The main contribution of this thesis is described in the included papers. The first paper handles symbol detection in MIMO communication. The paper shows ways to improve on the K-Best detection strategy from a hardware perspective. It focuses on how the inherent orthogonality between the real and the imaginary part of the complex number can be used. To do this a modified real-value decomposition is proposed together with a number of algorithm simplifications.
The second and third papers discusses a channel estimation algorithm known as Robust SVD channel estimation. This estimator can reach performance close to that of an MMSE estimator with a substantially reduced complexity. Paper II describes architectural considerations of the estimator and shows the implementation feasibility of the approach. In Paper III a hardware estimator architecture is presented, together with implementation data in a 130 nm process. The synthesized area is 1.38 mm2 with a maximum frequency of 179 MHz and a simulated average power dissipation of 14.2 mW.
In the fourth, fifth, and sixth paper another channel estimation algorithm, using matching pursuit, is analyzed and implemented. In Paper IV an improved matching pursuit algorithm is presented. It performs equally well to its predecessors while the complexity is reduced. The number of multiplications in the core estimation is reduced by ∼40 %. However, the algorithm requires a non-powerof-2 FFT/IFFT, with radix 3 and radix 5 units. Paper V describes the general strategy for implementing these type of FFT/IFFTs. It is seen that the complexity increases slightly when using radix 3 and radix 5 units but not dramatically. The number of multiplications per input data for a 52324 = 1200 point FFT is 14.1. This should be compared with 10.5 for the 210 = 1024 point and 12.0 for the 211 = 2048 point radix 2 FFTs respectively. Finally Paper VI describes the full implementation of the improved matching pursuit estimator, including the FFT/IFFT. Implemented in a low power 65 nm process, the estimator can be fit in an area of 1 mm2 and run at 70 MHz. The power dissipated is simulated to ∼13 mW at 50 MHz.
The main contribution of this thesis is described in the included papers. The first paper handles symbol detection in MIMO communication. The paper shows ways to improve on the K-Best detection strategy from a hardware perspective. It focuses on how the inherent orthogonality between the real and the imaginary part of the complex number can be used. To do this a modified real-value decomposition is proposed together with a number of algorithm simplifications.
The second and third papers discusses a channel estimation algorithm known as Robust SVD channel estimation. This estimator can reach performance close to that of an MMSE estimator with a substantially reduced complexity. Paper II describes architectural considerations of the estimator and shows the implementation feasibility of the approach. In Paper III a hardware estimator architecture is presented, together with implementation data in a 130 nm process. The synthesized area is 1.38 mm2 with a maximum frequency of 179 MHz and a simulated average power dissipation of 14.2 mW.
In the fourth, fifth, and sixth paper another channel estimation algorithm, using matching pursuit, is analyzed and implemented. In Paper IV an improved matching pursuit algorithm is presented. It performs equally well to its predecessors while the complexity is reduced. The number of multiplications in the core estimation is reduced by ∼40 %. However, the algorithm requires a non-powerof-2 FFT/IFFT, with radix 3 and radix 5 units. Paper V describes the general strategy for implementing these type of FFT/IFFTs. It is seen that the complexity increases slightly when using radix 3 and radix 5 units but not dramatically. The number of multiplications per input data for a 52324 = 1200 point FFT is 14.1. This should be compared with 10.5 for the 210 = 1024 point and 12.0 for the 211 = 2048 point radix 2 FFTs respectively. Finally Paper VI describes the full implementation of the improved matching pursuit estimator, including the FFT/IFFT. Implemented in a low power 65 nm process, the estimator can be fit in an area of 1 mm2 and run at 70 MHz. The power dissipated is simulated to ∼13 mW at 50 MHz.
Publishing year
2012
Language
English
Document type
Dissertation
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Keywords
- VLSI
- Digital Design
- ASIC
- Architecture
- Symbol Detection
- Channel Estimation
- MIMO
- OFDM
Status
Published
Supervisor
- Peter Nilsson
ISBN/ISSN/Other
- ISBN: 978-91-7473-367-9
Defence date
19 October 2012
Defence time
10:15
Defence place
Lecture hall E:1406, E-building, Ole Römers väg 3, Lund University Faculty of Engineering
Opponent
- Keshab Parhi (Professor)