Technology scaling impact on embedded ADC design for telecom receivers

Summary, in English

This paper is concerned with the impact of technology scaling on the choice of A/D converters in telecom receivers. It is shown that the trend of diminishing feature size, together with better matching of passive components, allows the use of A/D topologies traditionally confined to low-frequency, medium-resolution applications. The design of a 10 bit 20 MS/s ADC using the successive approximation algorithm is presented in order to validate the presented concepts. By using a deep-submicron technology, the speed of the chosen architecture is pushed to meet the desired output rate.

• Author: Jannik Nielsen; Pietro Andreani; Piero Malcovati; Andrea Baschirotto
• Publishing year: 2005
• Language: English
• Pages: 4614-4617
• Publication/Series: IEEE International Symposium on Circuits and Systems, 2005 (ISCAS).
• Volume: 5
• Links: http://ieeexplore.ieee.org/iel5/9898/31469/01465660.pdf; http://dx.doi.org/10.1109/ISCAS.2005.1465660
• Document type: Conference paper
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Status: Published
• ISBN/ISSN/Other: ISBN: 0-7803-8834-8