On Hardware Implementation of Radix 3 and Radix 5 FFT Kernels for LTE systems
Author
Summary, in English
Abstract in Undetermined
This paper treats the hardware architecture and
implementation of mixed radix FFTs with cores of radix 3 and
radix 5 in addition to the standard radix 2 core. The implementation
flow graphs of the higher radix cores are presented
together with a description of how these cores afTect a pipelined
FFT implementation. It is shown that the mixed radix FFT is
more expensive than the radix 2 implementation - a mixed radix
FFT of 1200 points require 36 real multipliers in a pipelined
implementation whereas a 2048 radix 2 FFT needs 30 real
multipliers. However, half of the multipliers in the mixed radix
case can be constant. Therefore it is still feasible to use the mixed
radix FFT if an algorithm calls for it.
This paper treats the hardware architecture and
implementation of mixed radix FFTs with cores of radix 3 and
radix 5 in addition to the standard radix 2 core. The implementation
flow graphs of the higher radix cores are presented
together with a description of how these cores afTect a pipelined
FFT implementation. It is shown that the mixed radix FFT is
more expensive than the radix 2 implementation - a mixed radix
FFT of 1200 points require 36 real multipliers in a pipelined
implementation whereas a 2048 radix 2 FFT needs 30 real
multipliers. However, half of the multipliers in the mixed radix
case can be constant. Therefore it is still feasible to use the mixed
radix FFT if an algorithm calls for it.
Publishing year
2011
Language
English
Publication/Series
[Host publication title missing]
Document type
Conference paper
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Conference name
29th Norchip conference, 2011
Conference date
2011-11-14 - 2011-11-15
Conference place
Lund, Sweden
Status
Published
ISBN/ISSN/Other
- ISBN: 978-1-4577-0514-4