A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility
Author
Summary, in English
This paper discusses design and measurements of
a flexible Viterbi decoder fabricated in 130-nm digital CMOS.
Flexibility was incorporated by providing various code rates and
modulation schemes to adjust to varying channel conditions.
Based on previous trade-off studies, flexible building blocks were
carefully designed to cause as little area penalty as possible. The
chip runs down to a minimal core supply of 0.8V. It turns out that
striving for more modulation schemes is beneficial in terms of
power consumption once the price is paid for accepting different
code rates viz. radices in the trellis and survivor path units.
a flexible Viterbi decoder fabricated in 130-nm digital CMOS.
Flexibility was incorporated by providing various code rates and
modulation schemes to adjust to varying channel conditions.
Based on previous trade-off studies, flexible building blocks were
carefully designed to cause as little area penalty as possible. The
chip runs down to a minimal core supply of 0.8V. It turns out that
striving for more modulation schemes is beneficial in terms of
power consumption once the price is paid for accepting different
code rates viz. radices in the trellis and survivor path units.
Publishing year
2008
Language
English
Pages
137-141
Publication/Series
Proceedings, Norchip Conference
Full text
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Document type
Conference paper
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Keywords
- Viterbi decoder
- CMOS
- flexible chips
- integrated circuits
Conference name
Norchip Conference, 2008
Conference date
2008-11-16 - 2008-11-17
Conference place
Talinn, Estonia
Status
Published
Project
- EIT_HSWC:Coding Coding, modulation, security and their implementation
Research group
- Informations- och kommunikationsteori
- Digital ASIC
- Telecommunication Theory