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Test Resource Partitioning and Optimization for SOC Designs

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Author

Summary, in English

We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the aim of minimizing the total test application time and the routing of the added TAM (test access mechanism) wires. A feature of our approach is that it pinpoints bottlenecks that are likely to limit the test solution, which is important in the iterative test solution development process. We demonstrate the usefulness of the technique through a comparison with a test scheduling and TAM design tool.

Publishing year

2003

Language

English

Pages

319-319

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • core-based design
  • resource floor-planning
  • test access mechanism
  • TAM
  • test scheduling
  • TAM routing

Conference name

2003 IEEE VLSI Test Symposium VTS03

Conference date

2003-04-27 - 2003-05-01

Conference place

Napa, CA, United States

Status

Published

ISBN/ISSN/Other

  • ISSN: 1093-0167
  • ISBN: 0-7695-1924-5