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Hardware architecture for matrix factorization in MIMO receivers

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Author

  • Barbara Cerato
  • Guido Masera
  • Peter Nilsson

Summary, in English

This paper presents the hardware realization of the factorization algorithm required in a MIMO OFDM receiver to make the detection and decoding a non-orthogonal space-time code. Requirements of a real scenario represented by the standard IEEE 802.11n for WLAN have been analyzed and exploited to draw out the specifications of the proposed implementation. A very high throughput hardware realization has been obtained able to factorize 128 8x8 real channel matrices during the channel updating period of 28 &3956;s, with a final throughput of 4,63 millions of matrices processed per second. Synthesis results on both 0.13 &3956;m CMOS standard cell technology and FPGA compare favourably to previous implementations.

Publishing year

2007

Language

English

Pages

196-199

Publication/Series

Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

17th ACM Great Lakes Symposium on VLSI (GLSVLSI), 2007

Conference date

2007-03-11 - 2007-03-13

Conference place

Stresa - Lago Maggiore, Italy

Status

Published

Research group

  • Elektronikkonstruktion

ISBN/ISSN/Other

  • ISBN: 978-1-59593-605-9