A single-stage direct interpolation multiphase clock generator with phase error averaging
Author
Summary, in English
Multiphase clock generators are conventionally implemented with a feedback loop. This paper presents a non-feedback approach to generate multiphase clocks. A simple architecture of direct phase interpolation is proposed, in which the edges of two phase-adjacent signals are used to control the discharge (or charge) of two capacitors respectively, producing time-overlapped slopes. A resistor chain connected to the two capacitors is used to interpolate a number of new slopes in between. The generated phase resolution depends on the number and ratios of resistors thus is not limited by an inverter delay. Based on this architecture, a multiphase clock generator is developed. In addition, a phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a 0.35 mum, 3.3 V CMOS process. The measured performance shows it can produce 8 evenly spaced clock signals in one input clock period and work in an input clock range from 300 MHz to 600 MHz. The measured maximum jitter performance is rms 6.8 ps and peak-to-peak 47 ps, respectively.
Publishing year
2004
Language
English
Pages
17-26
Publication/Series
Analog Integrated Circuits and Signal Processing
Volume
38
Issue
1
Document type
Journal article
Publisher
Springer
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Keywords
- multiphase
- non-feedback
- clock generator
- phase interpolation
Status
Published
ISBN/ISSN/Other
- ISSN: 0925-1030