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A 3.3V low-jitter frequency synthesizer applied to fast Ethernet transceiver

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Author

  • Ping Lu
  • Yan Wang
  • Lian Li
  • Juyan Ren

Summary, in English

A frequency synthesizer applied to 10/100 Base-T Ethernet transceiver is described. It can work in 10Mbps or 100Mbps mode adaptively and convert from one mode to another freely. The circuit can meet both requirements of transmitter on rising/falling time and receiver on CDR so that the additional power and area are saved. Under some testing circumstance, G of voltage control oscillator jittercycle-cycle is only 22ps with G of reference clock jittercycle-cycle 25ps (Herzel and Razavi, 1997). The testing result proves that the frequency synthesizer has good processing stability and rejection to noises. It works well for transmitter and receiver. The circuit is designed with SMIC 0.35μm standard CMOS technology and the power supply is 3.3V.

Publishing year

2005

Language

English

Pages

431-434

Publication/Series

[Host publication title missing]

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

The 6th International Conference on ASIC, ASICON 2005

Conference date

2005-10-24 - 2005-10-27

Conference place

Shanghai, China

Status

Published

ISBN/ISSN/Other

  • ISBN: 0-7803-9210-8