A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
Author
Summary, in English
Two branches of gated ring oscillators (GRO)
act as the delay lines in 2-dimension Vernier
time-to-digital converter (TDC). The proposed
architecture reduces dramatically the inherent latency of
vernier structure. The already small quantization noise of
the standard Vernier TDC is further first-order shaped by
the GRO operation. The TDC has been simulated in 90nm
CMOS technology. Operating from 50MHz reference
frequency, it achieves a resolution better than 2ps
assuming a signal bandwidth of 1.56MHz (OSR=16), for a
minimum current consumption of 1.8mA from 1.2V.
act as the delay lines in 2-dimension Vernier
time-to-digital converter (TDC). The proposed
architecture reduces dramatically the inherent latency of
vernier structure. The already small quantization noise of
the standard Vernier TDC is further first-order shaped by
the GRO operation. The TDC has been simulated in 90nm
CMOS technology. Operating from 50MHz reference
frequency, it achieves a resolution better than 2ps
assuming a signal bandwidth of 1.56MHz (OSR=16), for a
minimum current consumption of 1.8mA from 1.2V.
Department/s
Publishing year
2013
Language
English
Publication/Series
NORCHIP 2012
Document type
Conference paper
Publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Keywords
- Digitall PLL
- TDC
- GRO
- 2-dimention
Conference name
Norchip conference, 2012
Conference date
2012-11-12 - 2012-11-13
Conference place
Copenhagen, Denmark
Status
Published
Research group
- Analog RF
ISBN/ISSN/Other
- ISBN: 978-1-4673-2221-8
- ISBN: 978-1-4673-2223-2