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Temperature and annealing effects on InAs nanowire MOSFETs

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Author

Editor

  • Evangelos Gogolides

Summary, in English

We report on temperature dependence on the drive current as well as long-term effects of annealing in vertical InAs nanowire Field-Effect Transistors. Negatively charged traps in the HfO2 gate dielectric are suggested as one major factor in explaining the effects observed in the transistor characteristics. An energy barrier may be correlated with an un-gated InAs nanowire region covered with HfO2 and the effects of annealing may be explained by changed charging on defects in the oxide. Initial simulations confirm the general effects on the I-V characteristics by including fixed charge. (c) 2011 Elsevier B.V. All rights reserved.

Publishing year

2011

Language

English

Pages

1105-1108

Publication/Series

Microelectronic Engineering

Volume

88

Issue

7

Document type

Conference paper

Publisher

Elsevier

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Condensed Matter Physics

Keywords

  • InAs
  • Nanowire
  • FET
  • High-k
  • HfO2
  • MOSFET
  • III-V semiconductor
  • Annealing

Conference name

17th International Conference on Insultating Films on Semiconductors

Conference date

2011-06-21 - 2011-06-24

Conference place

Grenoble, France

Status

Published

Research group

  • Nano

ISBN/ISSN/Other

  • ISSN: 1873-5568
  • ISSN: 0167-9317