The browser you are using is not supported by this website. All versions of Internet Explorer are no longer supported, either by us or Microsoft (read more here: https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Please use a modern browser to fully experience our website, such as the newest versions of Edge, Chrome, Firefox or Safari etc.

An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint

På svenska

Author

Summary, in English

The quality of test is highly related to the number of faults that can be detected during the testing (fault coverage) and the defect probability of each testable unit. High test quality is reached by applying an excessive number of good test vectors, however, such a high test data volume can be problematic to fit in the ATE's (automatic test equipment) limited memory. We therefore propose, for core-based designs, a scheme that selects test vectors for each core, and schedule the test vectors in such a way that the test quality is maximized under a given test time constraint given by the ATE memory depth.

Publishing year

2004

Language

English

Pages

254-257

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • testing
  • fault coverage
  • defect probabilities
  • embedded systems

Conference name

2004 IEEE Asian Test Symposium ATS 2004

Conference date

0001-01-02

Status

Published

ISBN/ISSN/Other

  • ISSN: 1081-7735
  • ISBN: 0-7695-2235-1