High-level design flow for all-digital PLLs

Summary, in English

Deep-submicrometer CMOS processes are not suitable for traditional analog circuit design but they provide new opportunities of integrating complex digital functions. Within RF wireless communications, frequency synthesis stands out as a fundamental feature and novel digital solutions have been suggested for its implementation. Moving from an existing model, the goal of this paper is to outline the steps of a high-level approach to the design of an all-digital phase-locked loop (ADPLL)

• Author: Silvia Dondi; Roland Strandberg; Magnus Nilsson; Andrea Boni; Pietro Andreani
• Publishing year: 2006
• Language: English
• Pages: 247-250
• Publication/Series: 24th Norchip Conference, 2006.
• Links: http://ieeexplore.ieee.org/iel5/4126933/4075696/04126992.pdf; http://dx.doi.org/10.1109/NORCHP.2006.329221
• Document type: Conference paper
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Status: Published
• ISBN/ISSN/Other: ISBN: 1-4244-0772-9