A 0.13µm CMOS ΔΣ PLL FM Transmitter

Summary, in English

A short range FM transmitter is presented. It uses an architecture where the output frequency of a phase locked loop (PLL) is modulated by varying the division number of the feedback divider, using the 1-bit output of a ΔΣ ADC. The measured total harmonic distortion (THD) plus noise is less than 1% at 75 kHz deviation. The transmitter is fully integrated in a 0.13µm CMOS process and the core area is 0.24 mm2. The current consumption is 4.4mA from a 1.2V supply.

• Author: Ying Wu; Xiaodong Liu; Dawei Ye; Vijay Viswam; Lin Zhu; Ping Lu; Dejan Radjen; Henrik Sjöland
• Department/s: Department of Electrical and Information Technology; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publishing year: 2011
• Language: English
• Publication/Series: [Host publication title missing]
• Links: http://dx.doi.org/10.1109/NORCHP.2011.6126744
• Document type: Conference paper
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: 29th Norchip conference, 2011
• Conference date: 2011-11-14 - 2011-11-15
• Conference place: Lund, Sweden
• Status: Published
• ISBN/ISSN/Other: ISBN: 978-1-4577-0514-4