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A Technique for Test Infrastructure Design and Test Scheduling

På svenska

Author

Summary, in English

We propose a technique for test scheduling and design of test bus infrastructure where test application time and test bus length and width are minimized while constraints on power consumption and test resources are considered. Our approach is suitable for repeated use in the design space exploration process due to its low computational cost. For the final design, we use simulated annealing to optimize the solution. Our technique has been implemented and experimental results show the efficiency of our approach.

Publishing year

2000

Language

English

Pages

26-26

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • testing
  • simulated annealing
  • test scheduling
  • test bus infrastructure

Conference name

Design and Diagnostic of Electronic Circuits and Systems Workshop DDECS

Conference date

0001-01-02

Status

Published