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A 53.3 Mb/s 4x4 16-QAM MIMO Decoder in 0.35um CMOS

Author

  • Zhan Guo
  • Peter Nilsson

Summary, in English

An ASIC implementation of the K-best Schnorr-Euchner decoder is presented for a 4/spl times/4 16-QAM MIMO system. There are several low complexity and low power features incorporated in the proposed VLSI architecture. The chip is fabricated in a 0.35-/spl mu/m CMOS technology. The chip core area is 5.76 mm/sup 2/ with 91 K gates. Furthermore, the decoding throughput that the chip can support is up to 53.3 Mb/s with a core power consumption of 626 mW at 100 MHz clock frequency and 2.8 V supply. The corresponding decoding latency is 2.4 /spl mu/s.

Publishing year

2005

Language

English

Pages

4947-4950

Publication/Series

IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005.

Volume

5

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

IEEE International Symposium on Circuits and Systems (ISCAS), 2005

Conference date

2005-05-23 - 2005-05-26

Conference place

Kobe, Japan

Status

Published

Research group

  • Elektronikkonstruktion

ISBN/ISSN/Other

  • ISBN: 0-7803-8834-8