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A 5GHz 90-nm CMOS all digital phase-locked loop

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Author

Summary, in English

An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase-frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use delay line cells with uneven delay time. During frequency acquisition an automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks for both high resolution and wide frequency tuning range. To further increase the resolution a high-speed delta-sigma modulator is also used, modulating the DCO fine tuning word. The PLL achieves a measured phase noise of -125dBc/Hz at 1MHz offset from a divided-by-2 carrier frequency of 2.58GHz. The core area is 0.33mm2 and the current consumption is 30mA from a 1.2V supply.

Publishing year

2011

Language

English

Pages

49-59

Publication/Series

Analog Integrated Circuits and Signal Processing

Volume

66

Issue

1

Document type

Journal article

Publisher

Springer

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • RF
  • Digitally Controlled Oscillator (DCO)
  • Phase Locked Loop (PLL)
  • Time-to-Digital Converter (TDC)
  • All Digital Phase-Locked Loop (ADPLL)
  • CMOS

Status

Published

Research group

  • Analog RF
  • Data converters & RF

ISBN/ISSN/Other

  • ISSN: 0925-1030