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A low complexity architecture for binary image erosion and dilation using structuring element decomposition

Author

Summary, in English

This paper describes a new hardware architecture for binary image erosion and dilation. The design is to be used in a self contained real-time surveillance system. Thus, low complexity and low power consumption are main constraints. To achieve this goal the aim has been to reduce memory requirements and the number of memory accesses per pixel. By storing only the number of consecutive ones that appears horizontally and vertically in the input image, only two internal memory accesses per calculated output pixel are required. The number of memory accesses is independent of the size of the structuring element (SE) as long as it is rectangular and only contains ones, which is a common case. The internal memory size is proportional to log<sub>2</sub>(SE<sub>height</sub>), which means that a large span of SE sizes can be supported with a small amount of hardware

Publishing year

2005

Language

English

Pages

3431-3434

Publication/Series

IEEE International Symposium on Circuits and Systems (ISCAS)

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • structuring element decomposition
  • memory accesses per pixel
  • reduced memory requirements
  • power consumption
  • real-time surveillance system
  • image dilation
  • hardware architecture
  • low complexity architecture
  • binary image erosion

Conference name

IEEE International Symposium on Circuits and Systems (ISCAS), 2005

Conference date

2005-05-23 - 2005-05-26

Conference place

Kobe, Japan

Status

Published

Research group

  • Elektronikkonstruktion

ISBN/ISSN/Other

  • ISBN: 0-7803-8834-8