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A 2048 complex point FFT processor using a novel data scaling approach

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Author

Summary, in English

In this paper, a novel data scaling method for pipelined FFT processors is proposed. By using data scaling, the FFT processor can operate on a wide range of input signals without performance loss. Compared to existing block scaling methods, like implementations of Convergent Block Floating Point (CBFP), the memory requirements can be reduced while preserving the SNR. The FFT processor has been synthesized and sent for fabrication in a 0.35μm standard CMOS technology. In netlist simulations, the FFT processor is capable of calculating a 2048 complex point FFT or IFFT in 27μs with a maximum clock frequency of 76MHz.

Publishing year

2003

Language

English

Pages

45-48

Publication/Series

Proceedings - IEEE International Symposium on Circuits and Systems

Volume

4

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Data scaling

Conference name

IEEE International Symposium on Circuits and Systems (ISCAS '03), 2003

Conference date

2003-05-25 - 2003-05-28

Conference place

Bangkok, Thailand

Status

Published

ISBN/ISSN/Other

  • ISSN: 0271-4310
  • ISSN: 2158-1525
  • CODEN: PICSDI