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Hardware implementation of mapper for Faster-than-Nyquist signaling transmitter

Author

Summary, in English

This paper presents the implementation of the mapper block in a faster-than-Nyquist (FTN) signaling transmitter. The architecture is Look-Up Table (LUT) based and the complexity is reduced to a few adders and a buffer to store intermediate results. Two flavors of the architecture has been designed and evaluated in this article, one, a register based implementation for the buffer and the other using a Random Access Memory

(RAM). The tradeoff between the two is throughput versus area. The register based implementation is fast requiring only one clock cycle to complete the calculation (i.e a read, calculate and write back) for every incoming FTN symbol. However, it becomes

prohibitive when systems with large number of sub-carriers (>64) is considered. The RAM based implementation provides a better solution in terms of area with slightly lower throughput. The mapper has been targetted for both FPGA (Xilinx Virtex-II

Pro) and ASIC (130nm standard cell CMOS) implementations. The design has been successfully tested on the FPGA and its output verified with the reference MATLAB model.

Publishing year

2009

Language

English

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • hardware implementation
  • faster-than-Nyquist
  • multicarrier
  • transmitter

Conference name

Norchip Conference, 2009

Conference date

2009-11-16 - 2009-11-17

Conference place

Trondheim, Norway

Status

Published

Project

  • EIT_HSWC:Coding Coding, modulation, security and their implementation

Research group

  • Telecommunication Theory
  • Digital ASIC
  • Elektronikkonstruktion

ISBN/ISSN/Other

  • ISBN: 978-1-4244-4310-9