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Providing flexibility in a convolutional encoder

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Author

Summary, in English

In future radio systems, flexible coding and decoding architectures will be required. In case of the latter, implementing architectural flexibility with regard to low power issues is a challenging task. The flexible encoding platform in this paper is a first step toward this envisioned decoder. It generates a wide class of codes, starting with convolutional codes. As an extension to this, turbo codes will be included by adding an interleaver. At this prototyping stage, the system is implemented on an FPGA. The decision to choose the observer canonical form is defended by a thorough investigation of its critical path properties. Proper configuration allows code rates of b/c, b=1 ... 15, c=2 ... 16, b<c. Power can be saved by shutting down unused system modules

Publishing year

2003

Language

English

Pages

272-275

Publication/Series

Proceedings of the 2003 IEEE International Symposium on Circuits and Systems (Cat. No.03CH37430)

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • low power systems
  • convolutional codes
  • turbo codes
  • FPGA implementation
  • interleaver
  • observer canonical form critical path properties
  • code rates
  • unused system module shut down
  • wireless personal area networks
  • radio systems
  • flexible coding/decoding architectures
  • convolutional encoder flexibility
  • WPAN
  • power saving

Conference name

IEEE International Symposium on Circuits and Systems (ISCAS '03), 2003

Conference date

2003-05-25 - 2003-05-28

Conference place

Bangkok, Thailand

Status

Published

Research group

  • Elektronikkonstruktion

ISBN/ISSN/Other

  • ISBN: 0-7803-7761-3