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A Distributed Architecture to Check Global Properties for Post-Silicon Debug

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Author

Summary, in English

Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking global properties that are distributed on the chip. In this paper we define an architecture to non-intrusively observe global properties at run time using distributed monitors. The architecture enables to perform actions when a property holds, such as stopping (part of) the system for inspection. We apply this architecture to the problem of software races that result in incorrect communication between concurrent tasks on different processors. In a case study, where we implemented monitors, event distribution, and instruments to stop communication between intellectual property (IP) blocks, we demonstrate that these races can be detected and classified as timing violations or as FIFO protocol violations.

Publishing year

2010

Language

English

Publication/Series

Test Symposium (ETS), 2010 15th IEEE European

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

IEEE European Test Symposium (ETS'10), 2010

Conference date

2010-05-24 - 2010-05-28

Conference place

Prague, Czech Republic

Status

Published

ISBN/ISSN/Other

  • ISBN: 978-1-4244-5834-9