Single InAs/GaSb Nanowire Low-Power CMOS Inverter
Author
Summary, in English
III − V semiconductors have so far predom-
inately been employed for n-type transistors in high-frequency
applications. This development is based on the advantageous
transport properties and the large variety of heterostructure
combinations in the family of III − V semiconductors. In
contrast, reports on p-type devices with high hole mobility
suitable for complementary metal − oxide − semiconductor
(CMOS) circuits for low-power operation are scarce. In
addition, the di ffi culty to integrate both n- and p-type devices
on the same substrate without the use of complex bu ff er layers
has hampered the development of III − V based digital logic.
Here, inverters fabricated from single n-InAs/p-GaSb hetero-
structure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high- κ
dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and
o ff -state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold
swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V ds = 0.5 V. Inverter characteristics display a full signal swing
and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although
large parasitic capacitances deform the waveform at higher frequencies.
inately been employed for n-type transistors in high-frequency
applications. This development is based on the advantageous
transport properties and the large variety of heterostructure
combinations in the family of III − V semiconductors. In
contrast, reports on p-type devices with high hole mobility
suitable for complementary metal − oxide − semiconductor
(CMOS) circuits for low-power operation are scarce. In
addition, the di ffi culty to integrate both n- and p-type devices
on the same substrate without the use of complex bu ff er layers
has hampered the development of III − V based digital logic.
Here, inverters fabricated from single n-InAs/p-GaSb hetero-
structure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high- κ
dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and
o ff -state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold
swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V ds = 0.5 V. Inverter characteristics display a full signal swing
and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although
large parasitic capacitances deform the waveform at higher frequencies.
Department/s
Publishing year
2012
Language
English
Publication/Series
Nano Letters
Document type
Journal article
Publisher
The American Chemical Society (ACS)
Topic
- Nano Technology
Keywords
- Nanowire
- inverter
- InAs/GaSb
- low-power operation
- III-V CMOS
Status
Published
ISBN/ISSN/Other
- ISSN: 1530-6992