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An Integrated System-On-Chip Test Framework

På svenska

Author

Summary, in English

In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.

Publishing year

2001

Language

English

Pages

138-144

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • testing
  • system-on-chip
  • test access mechanism selection
  • test parallelization
  • test resource placement
  • power consumption
  • embedded systems

Conference name

Design, Automation and Test in Europe DATE Conference

Conference date

2001-03-13 - 2001-03-16

Conference place

Munich, Germany

Status

Published

ISBN/ISSN/Other

  • ISSN: 1530-1591
  • ISBN: 0-7695-0993-2