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A low logic depth complex multiplier

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Author

Summary, in English

A complex multiplier has been designed for use in a pipelined fast fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input to output delay as short as possible. A new architecture based on distributed arithmetic and Wallace-trees has been developed and is compared to a previous multiplier realized as a regular distributed arithmetic array. The simulated gain in speed for the presented multiplier is about 100%. For verification, the multiplier is fabricated in a three metal-layer 0.5µ CMOS process using a standard cell library. The fabricated multiplier chip has been functionally verified.

Publishing year

1998

Language

English

Pages

204-207

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

European Solid-State Circuits Conference (ESSCIRC), 1998

Conference date

1998-09-22 - 1998-09-24

Conference place

Hague, Netherlands

Status

Published