Power optimization of a reconfigurable FIR-filter

Summary, in English

This paper describes power optimization techniques applied to a reconfigurable digital finite impulse response (FIR) filter used in a Universal Mobile Telephone Service (UMTS) mobile terminal. Various methods of optimization for implementation were combined to achieve low cost in terms of power consumption. Each optimization method is described in detail and is applied to the reconfigurable filter. The optimization methods have achieved a 78.8% reduction in complexity for the multipliers in the FIR structure. A comparison of synthesized RTL models of the original and the optimized architectures resulted in a 27% reduction in look-up tables when targeted for the Xilinx Virtex II Pro field programmable gate array (FPGA). An automated method for transformation of coefficient multipliers into bit-shifts is also presented

• Author: H Bruce; R Veljanovski; Viktor Öwall; J Singh
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2004
• Language: English
• Pages: 321-324
• Publication/Series: 2004 IEEE Workshop on Signal Processing Systems Design and Implementation
• Links: http://dx.doi.org/10.1109/SIPS.2004.1363070
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Keywords: field programmable gate array; Xilinx Virtex II Pro; look-up tables; synthesized RTL models; power consumption; UMTS mobile terminal; Universal Mobile Telephone Service; digital finite impulse response filter; power optimization; reconfigurable FIR-filter; FPGA; coefficient multipliers; bit-shifts; automated method
• Conference name: 2004 IEEE Workshop on Signal Processing Systems Design and Implementation
• Conference date: 2004-10-13 - 2004-10-15
• Conference place: Austin, TX, United States
• Status: Published
• ISBN/ISSN/Other: ISBN: 0-7803-8504-7