Design and Measurement of a Variable-Rate Viterbi Decoder in 130-nm Digital CMOS
Author
Summary, in English
This paper discusses design and measurements of a flexible Viterbi decoder
fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing
various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.
fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing
various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.
Department/s
Publishing year
2010
Language
English
Pages
129-137
Publication/Series
Microprocessors and Microsystems
Volume
34
Issue
2010
Full text
- Available as PDF - 999 kB
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Document type
Journal article
Publisher
Elsevier
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Status
Published
Project
- PCC: Algorithm and Hardware
Research group
- Elektronikkonstruktion
- Digital ASIC
- Telecommunication Theory
ISBN/ISSN/Other
- ISSN: 0141-9331