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Reducing Leakage Power in Fixed Coefficient Arithmetic

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Author

  • Peter Nilsson

Summary, in English

Most of the power consumption has in the past been related to the dynamic activities, in a CMOS circuit. However, the static power, i.e. leakage, is a major contribution to the total power consumption, in present nano-meter scale technologies. This paper discusses static power reduction methodologies on architectural and arithmetical level. Novel arithmetic techniques to reduce the static power consumption in digital applications for nano-scale CMOS technologies are addressed. An arithmetic reduction of the static power consumption down to 5 % by using bit-serial arithmetic compared to bit-parallel is indicated.

Publishing year

2007

Language

English

Pages

306-309

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

IEEE 14th International Conference on Electronics, Circuits and Systems (ICECS 2007)

Conference date

2007-12-11 - 2007-12-14

Conference place

Marrakech, Morocco

Status

Published

Research group

  • Elektronikkonstruktion