A hybrid interconnect network-on-chip and a transaction level modeling approach for reconfigurable computing

Summary, in English

This paper presents a hybrid interconnect network consisting of a local network with dedicated wires and a global hierarchical network. A distributed memory approach enables the possibility to use generic memory banks as routing buffers, simplifies the implementation and reduces the area requirements of routers. A SystemC simulation environment (SCENIC) has been developed to simulate and instrument models, and to setup different topologies and scenarios. Modules are designed as transaction level models to improve design time and simulation speed.

• Author: Thomas Lenart; Henrik Svensson; Viktor Öwall
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2008
• Language: English
• Pages: 398-404
• Publication/Series: [Host publication title missing]
• Full text: - 516 kB; Download statistics
• Links: http://dx.doi.org/10.1109/DELTA.2008.85
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: IEEE International Symposium on Electronic Design, Test & Applications (DELTA)
• Conference date: 2008-01-23 - 2008-01-25
• Status: Published
• Research group: Digital ASIC
• ISBN/ISSN/Other: ISBN: 978-0-7695-3110-6