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Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling

Author

  • Soheil Samii
  • Erik Larsson
  • Krishnendu Chakrabarty
  • Zebo Peng

Summary, in English

Concurrent testing of the cores in a modular core-based System-on-Chip reduces the test application time but increases the test power consumption. Power models and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated by a core when tested, is pessimistic but simple for a scheduling algorithm to handle. In this paper, we propose a cycle-accurate power model with a power value per clock cycle and a corresponding scheduling algorithm. The model takes into account the switching activity in the scan chains caused by both the test stimuli and the test responses during scan-in, launch-and-capture, and scan-out. Further, we allow a unique power model per wrapper chain configuration as the activity in a core will be different depending on the number of wrapper chains at a core. Extensive experiments on ITC'02 benchmarks and an industrial design show that the testing time can be substantially reduced (on average 16.5% reduction) by using the proposed cycle-accurate test power model.

Publishing year

2006

Language

English

Pages

1-32

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • testing
  • system-on-chip
  • test scheduling
  • power modelling

Conference name

IEEE International Test Conference ITC '06

Conference date

2006-10-24 - 2006-10-26

Conference place

Santa Clara, CA, United States

Status

Published

ISBN/ISSN/Other

  • ISSN: 1089-3539
  • ISBN: 1-4244-0292-1