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FPGA implementation of controller-datapath pair in custom image processor design

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Author

Summary, in English

In order to reduce the effort of the controller design in the customized image convolution processor, a controller synthesis tool is developed based on [9] to support the design flow from a system or algorithm specification to RTL level VHDL. Architecture extensions to basic FSMs structures are implemented with the purpose of optimizing controller design for area and power consumption. Together with controller implementation, a custom datapath architecture with three level memory hierarchies is developed aiming at a real-time power efficient image processing solution with low I/O bandwidth requirements. The complete design is prototyped on Xilinx Virtex 2 platform with comparable performance with that of TI C64x processor at only 2/15 of its clock frequency.

Publishing year

2004

Language

English

Pages

141-144

Publication/Series

Proceedings of the 2004 International Symposium on Circuits and Systems

Volume

5

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Line memories
  • Image processors
  • Clock cycles
  • Image size

Conference name

IEEE International Symposium on Circuits and Systems (ISCAS), 2004

Conference date

2004-05-23 - 2004-05-26

Conference place

Vancouver, BC, Canada

Status

Published

ISBN/ISSN/Other

  • ISSN: 0271-4310
  • ISSN: 2158-1525