An arbitrarily skewable multiphase clock generator combining direct interpolation with phase error average

Summary, in English

A multiphase clock generator based on direct phase interpolation is presented. No feedback loop is required. A simple phase interpolation architecture is proposed, in which the two phase-adjacent signals are interpolated by using a series of resistors via inverters' discharging or charging slopes to generate multiphase outputs in a single stage. A phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The measured performance shows it can operate at the input clock frequencies from 300 MHz to 600 MHz and has the rms jitter of 6 ps at 500 MHz.

• Author: Yang Lixin; Jiren Yuan
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2003
• Language: English
• Pages: 645-648
• Publication/Series: Proceedings - IEEE International Symposium on Circuits and Systems
• Volume: 1
• Links: http://dx.doi.org/10.1109/ISCAS.2003.1205646
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Keywords: Multiphase clock generators
• Conference name: Proceedings of the 2003 IEEE International Symposium on Circuits and Systems
• Conference date: 2003-05-25 - 2003-05-28
• Conference place: Bangkok, Thailand
• Status: Published
• ISBN/ISSN/Other: ISSN: 0271-4310; ISSN: 2158-1525; CODEN: PICSDI