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Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints

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Author

  • Farrokh Ghani Zadegan
  • Urban Ingelsson
  • Golnaz Asani
  • Gunnar Carlsson
  • Erik Larsson

Summary, in English

In contrast to IEEE 1149.1, IEEE P1687 allows, through segment insertion bits, flexible scan paths for accessing on-chip instruments, such as test, debug, monitoring, measure- ment and configuration features. Flexible access to embedded instruments allows test time reduction, which is important at production test. However, the test access scheme should be carefully selected such that resource constraints are not violated and power constraints are met. For IEEE P1687, we detail in this paper session-based and session-less test scheduling, and propose resource and power-aware test scheduling algorithms for the detailed scheduling types. Results using the implementation of our algorithms shows on ITC’02-based benchmarks significant test time reductions when compared to non-optimized test schedules.

Publishing year

2011

Language

English

Pages

525-531

Publication/Series

2011 Asian Test Symposium

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Test Scheduling
  • Constraints
  • IEEE P1687
  • IJTAG

Conference name

Test Symposium (ATS), 2011 20th Asian

Conference date

2011-11-20

Conference place

New Delhi, India

Status

Published

Research group

  • Digital ASIC

ISBN/ISSN/Other

  • ISSN: 1081-7735
  • ISBN: 978-1-4577-1984-4