Design Automation for IEEE P1687

Summary, in English

The IEEE P1687 (IJTAG) standard proposal aimsat standardizing the access to embedded test and debug logic(instruments) via the JTAG TAP. P1687 specifies a componentcalled Segment Insertion Bit (SIB) which makes it possible toconstruct a multitude of alternative P1687 instrument accessnetworks for a given set of instruments. Finding the best accessnetwork with respect to instrument access time and the numberof SIBs is a time-consuming task in the absence of EDA support.This paper is the first to describe a P1687 design automationtool which constructs and optimizes P1687 networks. Our EDAtool, called PACT, considers the concurrent and sequential accessschedule types, and is demonstrated in experiments on industrialSOCs, reporting total access time and average access time.

• Author: Farrokh Ghani Zadegan; Urban Ingelsson; Gunnar Carlsson; Erik Larsson
• Publishing year: 2011
• Language: English
• Publication/Series: 2011 Design, Automation & Test in Europe
• Links: http://dx.doi.org/10.1109/DATE.2011.5763228
• Document type: Conference paper
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: Design, Automation and Test in Europe (DATE 2011),
• Conference date: 0001-01-02
• Status: Published
• ISBN/ISSN/Other: ISBN: 978-1-61284-208-0