Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
Author
Summary, in English
Publishing year
2008
Language
English
Pages
188-193
Publication/Series
[Host publication title missing]
Document type
Conference paper
Publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Keywords
- testing
- system-on-chip
- test-architecture optimization
- test scheduling
- test patterns
- compression
- test access mechanism
- TAM
- SOC
Conference name
Design, Automation, and Test in Europe DATE 2008
Conference date
2008-03-10 - 2008-03-14
Conference place
Munich, Germany
Status
Published
ISBN/ISSN/Other
- ISBN: 978-3-9810801-3-