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Low power analog channel decoder in sub-threshold 65nm CMOS

Author

Summary, in English

This paper presents the architecture and the corresponding

simulation results for a very low power half-rate

extended Hamming (8,4) decoder implemented in analog integrated

circuitry. TI’s 65nm low power CMOS design library

was used to simulate the complete decoder including an input

interface, an analog decoding core and an output interface. The

simulated bit error rate (BER) performance of the decoder is

presented and compared to the ideal performance expected from

the Hamming code. Transistor-level simulation results suggest

that a high throughput Hamming decoder up to 1 Mbits can be

implemented in analog circuits with a core power consumption

as low as 6 μW.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • sub-threshold CMOS
  • integrated circuits
  • low power circuits
  • Decoders

Conference name

Swedish System-on-Chip Conference 2010 (SSoCC'10)

Conference date

2010-05-03 - 2010-05-04

Conference place

Kolmården, Sweden

Status

Published

Research group

  • Telecommunication Theory
  • Digital ASIC
  • Analog RF
  • Elektronikkonstruktion