A 3-level asynchronous protocol for a differential two-wire communication link
Author
Summary, in English
A differential two-wire communication link with a 3-level asynchronous protocol is introduced. The proposed 3-level code contains information of both data and clock. Since only one edge is needed for each bit, the bandwidth of a link is efficiently utilized. The power consumption is reduced by the low-swing differential two-wire link and is further reduced by a 3-level code. The speed of the protocol is expected to reach 1 Gb/s in a 1.2-μm CMOS process.
Publishing year
1994
Language
English
Pages
1129-1132
Publication/Series
IEEE Journal of Solid-State Circuits
Volume
29
Issue
9
Document type
Journal article
Publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Keywords
- CMOS integrated circuits
- clocks
- decoding
- digital communication systems
- digital integrated circuits
- encoding
- protocols
- pulse-code modulation links
- telecommunication links
Status
Published
ISBN/ISSN/Other
- ISSN: 0018-9200