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Balancing BlockRAM and distributed RAM

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Author

Summary, in English

Xilinx FPGAs offer both Block SelectRAM and distributed RAM for embedded memory. To investigate the impact of utilizing such opportunities, some variations on the hardware implementation of a SNOW 2.0 stream cipher IP core have been designed. We find the ratio of throughput and effective slice usage to be close to 3.5. This allows a flexible trade-off between speed and area consumption, with a throughput between 7200 and 8000 Mbps and a slice usage between 900 and 2400 for Xilinx Virtex II and 4.

Publishing year

2005

Language

English

Publication/Series

Proceedings SSoCC 2005

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

Swedish System-on-Chip Conference (SSoCC'05)

Conference date

2005-04-18 - 2005-04-19

Conference place

Tammsvik, Sweden

Status

Published