Low Power Optimization of Bit-Serial Digital Filters

Summary, in English

A new approach to optimize full custom, fixed coefficient bit-serial filters aimed at high sample rate and low power consumption is presented. The idea is to trade the filter order with the coefficient length. To show the results two filters were designed and implemented, one as a minimum order filter and the other as a minimum coefficient filter. Measurements shows that a ten fold increase in sample rate can be obtained at half the power consumption

• Author: Pontus Åström; Peter Nilsson; Mats Torkelson
• Department/s: Department of Electrical and Information Technology; Departments at LTH
• Publishing year: 1997
• Language: English
• Pages: 229-232
• Publication/Series: Tenth Annual IEEE International ASIC Conference and Exhibit, 1997. Proceedings.
• Links: http://dx.doi.org/10.1109/ASIC.1997.617011
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: Tenth Annual IEEE International ASIC Conference and Exhibit (ASIC’97)
• Conference date: 1997-09-07 - 1997-09-10
• Conference place: Portland, Oregon, United States
• Status: Published
• Research group: Elektronikkonstruktion
• ISBN/ISSN/Other: ISBN: 0-7803-4283-6