Hardware Support for CSP on a Java Chip-Multiprocessor

Summary, in English

Due to memory bandwidth limitations, chip multiprocessors (CMP) adopting the convenient shared memory model for their main memory architecture scale poorly. On-chip core-to-core communication is a solution to this problem, that can lead to further performance increase for a number of multithreaded applications. Programmatically, the Communicating Sequential Processes (CSP) paradigm provides a sound computational model for such an architecture with message based communication. In this paper we explore hardware support for CSP in the context of an embedded Java CMP. The hardware support for CSP are on-chip communication channels, implemented by a ring-based network-on-chip (NoC), to reduce the memory bandwidth pressure on the shared memory. The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. CMP architectures of three to eight processors were implemented and tested on both Altera (EP1C12, EP2C70) and Xilinx (XC3S1200e) FPGAs, showing that the NoC accounts for under 9% of the total device area used by the system. Compared to shared memory-based communication, our NoC-based solution is between 1.7 and 9.3 times faster for raw data transfer, depending on the communication and memory configuration. Application speed-up, on the other hand, is highly dependent on the type of processing, as our measurements show.

• Author: Flavius Gruian; Martin Schoeberl
• Department/s: Department of Computer Science; ELLIIT: the Linköping-Lund initiative on IT and mobile communication; Parallel Systems
• Publishing year: 2013
• Language: English
• Pages: 472-481
• Publication/Series: Microprocessors and Microsystems
• Volume: 37
• Issue: 4-5
• Links: http://dx.doi.org/10.1016/j.micpro.2012.08.004
• Document type: Journal article
• Publisher: Elsevier
• Topic: Computer Science
• Status: Published
• Research group: ESDLAB
• ISBN/ISSN/Other: ISSN: 0141-9331