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A parallel 2Gops/s image convolution processor with low I/O bandwidth

Author

Summary, in English

A customized image processor for real time convolution of an image has been developed. Image convolution requires an extensive amount of calculation capacity and I/O communication which is hard to sustain with standard processors in real time. Therefore, a customized processor has been designed with a tailored architecture. The processors have a total sustained calculation capacity of >2G arithmetic operations/s at 20 MHz clock frequency, surpassing that of TMS320C80 for this application due to the tailored architecture.

Publishing year

1995

Language

English

Pages

87-90

Publication/Series

[Host publication title missing]

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

IEEE ASIC Conference and Exhibit

Conference date

1995-09-18 - 1995-09-22

Conference place

Austin, TX, United States

Status

Published

ISBN/ISSN/Other

  • ISSN: 1063-0988
  • ISBN: 0-7803-2707-1