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A CMOS 500 MS/S charge sampler

Author

  • Gang Xu
  • Jiren Yuan

Summary, in English

A new sample-and-hold circuit based on the charge sampling technique is introduced, which integrates input current instead of tracking input voltage to realize high speed and low voltage sampling. Both the theoretical analysis and the experimental results prove that it can realize both sample-and-hold and amplification functions. A 500 MS/s charge sampling circuit is implemented in 0.25 μm CMOS process and measured. The dynamic range reaches 42 dB within the 250 MHz bandwidth. The power consumption is about 5 mW.

Publishing year

2004

Language

English

Pages

462-466

Publication/Series

Proceedings of the IASTED International Conference on Circuits, Signals, and Systems

Document type

Conference paper

Publisher

ACTA Press

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Power consumption
  • Current mode sampling
  • Charge sampling
  • Charge sampler

Conference name

IASTED International Conference on Circuits, Signals, and Systems, 2004

Conference date

2004-11-28 - 2004-12-01

Conference place

Clearwater Beach, FL, United States

Status

Published

ISBN/ISSN/Other

  • ISBN: 0889864551