Design of highly-parallel, 2.2Gbps throughput signal detector for MIMO systems

Summary, in English

This paper presents a field-programmable gate array (FPGA) implementation of a new multiple-input multiple-output (MIMO) signal detection algorithm applicable to ultra-high throughput MIMO communication systems. The algorithm simplifies the computation significantly compared to traditional K-Best algorithm, and with negligible bit error ratio (BER) degradation. A highly-parallel structure is implemented on the Xilinx Virtex-4 (XC4VLX200) platform, which achieves 2.2 Gbps detection throughput and is about four times over previous implementation. Moreover, a pre-processing method is realized to reduce the number of multipliers inside the detector and shrinks the critical path delay down to 6.79 ns. Together with candidate-sharing-architecture to further save the hardware cost, a high speed, compact signal detector for MIMO systems is demonstrated.

• Author: Liang Liu; Xiaojing Ma; Fan Ye; Junyan Ren
• Publishing year: 2008
• Language: English
• Pages: 742-745
• Publication/Series: [Host publication title missing]
• Links: http://dx.doi.org/10.1109/ICC.2008.145
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: IEEE International Conference on Communications ICC 2008
• Conference date: 2008-05-19 - 2008-05-23
• Conference place: Beijing, China
• Status: Published
• ISBN/ISSN/Other: ISBN: 978-1-4244-2075-9