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Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain

Author

Summary, in English

This paper presents an analysis on energy dissipation

of digital half-band filters operating in the sub-threshold

(sub-VT) region with throughput and supply voltage constraints.

A 12-bit filter is implemented along with various unfolded

structures, used to form a decimation filter chain. The designs

are synthesized in a 65 nm low-leakage CMOS technology with

various threshold voltages. A sub-VT energy model is applied to

characterize the designs in the sub-VT domain. The results show

that the low-leakage standard-threshold technology is suitable

for the required throughput range between 250Ksamples/s and

2Msamples/s, at a supply voltage of 260mV. The total energy

dissipation of the filter is 205 fJ per sample.

Publishing year

2011

Language

English

Pages

837-840

Publication/Series

2011 IEEE International Symposium on Circuits and Systems (ISCAS)

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • CMOS
  • sub-threshold
  • 65 nm
  • Sub-VT
  • Chain
  • low power
  • Ultra Low energy
  • Decimation Filter
  • Digital

Conference name

IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011

Conference date

2011-05-15 - 2011-05-18

Conference place

Rio de Janeiro, Brazil

Status

Published

Research group

  • Digital ASIC
  • Analog RF
  • Elektronikkonstruktion

ISBN/ISSN/Other

  • ISSN: 0271-4310
  • ISSN: 2158-1525