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An 8-Bit, 100-MHz low glitch interpolation DAC

Author

  • Zhou Yijun
  • Jiren Yuan

Summary, in English

This paper describes an 8-Bit, 100-MHz current steering CMOS low glitch interpolation digital to analog converter (DAC). It includes a 16-tap voltage controlled delay line and 8-Bit based linear interpolators, making the effective clock rate up to 1.6-GHz. With the linear interpolation, the requirement on the analog reconstruction filter is relaxed, and low glitch digital to analog conversion is achieved. The chip is fabricated with a 3.3 V, 0.35 μm digital CMOS process

Publishing year

2001

Language

English

Pages

116-119

Publication/Series

Proceedings of the 2001 IEEE International Symposium on Circuits and Systems

Volume

4

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

IEEE International Symposium on Circuits and Systems, ISCAS, 2001

Conference date

2001-05-06 - 2001-05-09

Conference place

Sydney, NSW, Australia

Status

Published

ISBN/ISSN/Other

  • ISBN: 0-7803-6685-9